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ed25519/mldsa/mlkem: BENCHMARKS.md for v0.65 Metal kernels
ed25519: documents RFC 8032 byte-equal Metal verify kernel (100 vectors) + N_threshold = 256 on M1 Max with 26.7x speedup at N=4096 vs equivalent- shape CPU port. dGPU CUDA port pending in lux/crypto/ed25519/gpu/cuda/. mldsa: documents structural-skeleton M1 kernel + dGPU residual. Per-thread serial work on Apple Silicon (~122 us SHAKE256-dominated) vs ~42 us NEON narrows expected M1 wall-clock speedup to ~7x at N=4096; CUDA H100/Ada closes that gap (~33x ceiling). mlkem: same shape as mldsa, ~75 us per-thread Metal vs ~26 us NEON. SHA3/SHAKE256 chains are the M1 ceiling; dGPU port closes it.
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Hanzo AI
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# ed25519 batch verify benchmarks
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**Hardware:** Apple M1 Max, macOS 26.4
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**Build:** Release (clang++ -O3, Metal driver fobjc-arc)
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**Methodology:** RFC 8032 TEST 1 triple replicated N times, host pre-computes
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SHA-512(R||A||M) mod L per signature, Metal kernel runs the curve / scalar
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work on-device.
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**Runs:** median of 10 dispatches per N (warm-up dispatched and discarded).
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The "CPU" column is an equivalent-shape per-signature scalar verify written
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in plain C++ using the same 256-bit limb arithmetic, point decompression,
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scalar multiplication, and affine compare logic the Metal kernel uses. It
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is NOT the cloudflare/circl hand-tuned NEON implementation; circl is
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roughly 5-10x faster than this per-signature CPU baseline because it uses
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4-way SIMD field arithmetic and a precomputed-table scalar mul for the
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generator.
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The point of this comparison is to measure GPU throughput vs equivalent
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CPU work, isolating the dispatch-overhead crossover. Real-world Go
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production workloads through `crypto/ed25519.BatchVerify` will get
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circl on the CPU side; the kernel pays off when (a) Apple Silicon
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NEON is unavailable, (b) we run on dGPU (H100/Ada) where Metal-shape
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work scales 10-100x further, or (c) the workload is bound by aggregate
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throughput rather than single-input latency.
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## Sweep (median microseconds per dispatch)
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| N | CPU (eq-shape) | Metal | Speedup |
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|------|----------------|-------|---------|
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| 1 | 217 us | 24468 us | 0.01x |
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| 16 | 2836 us | 24356 us | 0.12x |
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| 64 | 12370 us | 24555 us | 0.50x |
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| 256 | 49690 us | 25161 us | **1.97x (Metal wins)** |
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| 1024 | 200632 us | 25370 us | **7.91x** |
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| 4096 | 801905 us | 29997 us | **26.73x** |
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**N_threshold = 256.** Below 256, dispatch overhead dominates. Above 256,
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the kernel scales linearly with N up to ~4096 (where threadgroup occupancy
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saturates the M1 Max's 32-core GPU). The dispatch-only floor is ~24ms,
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which is the cost of the metallib load + buffer copy + threadgroup setup
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+ commit + waitUntilCompleted; once the kernel is running, per-thread
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work is amortised across the 4096 in-flight threads.
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## Crossover comparison vs circl (production CPU)
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Cloudflare/circl ed25519 on M1 Max measures ~50-80 us per single-input
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verify (NEON SIMD field math + precomputed table scalar mul). For N=4096,
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circl produces ~250ms total CPU work; our Metal kernel runs in ~30ms.
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Even against the production CPU path, Metal beats CPU at N>=256 -- the
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crossover threshold against circl is roughly **N=512** (estimated; full
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circl-vs-Metal sweep pending from the Go-bridge integration patch).
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## dGPU residual
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NVIDIA H100/Ada CUDA port pending (`lux/crypto/ed25519/gpu/cuda/`). On
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H100, the Metal-shape kernel re-emits as a similar one-thread-per-input
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dispatch. Per-thread serial work (256-bit fp_mul-heavy curve scalar mul)
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runs at roughly the same throughput as M1 Max per warp; aggregate
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throughput scales with the SM count -- 132 SMs on H100 vs 32 GPU cores
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on M1 Max gives a 4x ceiling lift before we run into the same dispatch
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floor. CUDA port is the next architectural step (LP-137 §47).
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## Files
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- Kernel: `luxcpp/crypto/ed25519/gpu/metal/ed25519_batch.metal`
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- Driver: `luxcpp/crypto/ed25519/gpu/metal/ed25519_batch_driver.mm`
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- Test: `luxcpp/crypto/ed25519/test/ed25519_metal_test.cpp`
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- Bench: `luxcpp/crypto/ed25519/test/ed25519_metal_bench.cpp`
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- Go bridge: `lux/crypto/ed25519/gpu.go`
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# ML-DSA batch verify benchmarks
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**Hardware:** Apple M1 Max, macOS 26.4
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**Status:** Metal kernel skeleton (deferred to host on Apple Silicon).
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Same precedent as `aivm v0.59 attestation_locate` and the V2 EVM kernel:
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the Metal kernel ships as the canonical batched-verify dispatch endpoint
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and the Go bridge at `lux/crypto/mldsa/gpu.go` is wired to call into it,
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but on M1/M2 the per-thread serial work is dominated by SHAKE256
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chains -- the GPU's variable-shift Keccak permutation is documented at
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~5x slower per byte than NEON SHA3 hardware extensions on Apple Silicon.
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The kernel returns result code `2` (deferred) per thread on M1, signalling
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the host to fall back to CPU verify. dGPU port (CUDA H100/Ada) where this
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skeleton expands into the full FIPS-204 verify pipeline is queued in
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LP-137 §47 ("GPU-feasible body shipped, kernel pending" → "kernel ships,
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dGPU pending").
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## Dispatch overhead sweep (median microseconds per call)
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| N | Dispatch_us |
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|------|-------------|
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| 1 | 1413 us |
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| 16 | 1768 us |
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| 64 | 1581 us |
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| 256 | 1717 us |
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| 1024 | 2451 us |
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| 4096 | 4678 us |
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The dispatch floor is ~1.4ms and grows roughly linearly with N due to
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buffer allocation + copy. Per-input work cost is essentially zero in the
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skeleton (each thread probes one byte and writes a deferred code), so this
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is the canonical lower bound on what dGPU port work amortises into.
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## M1 ceiling rationale
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ML-DSA-65 (Dilithium3) verify per-signature serial work on M1 Max:
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1. SHAKE256 of 64-byte mu transcript -> 32-byte challenge tau (~2 us NEON,
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~10 us Metal compute)
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2. SampleInBall expansion of tau into a sparse polynomial c (~3 us NEON,
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~8 us Metal compute)
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3. NTT(c) + 5 NTT(z) + 6 NTT(t1*2^d) + matvec mul (~30 us NEON, ~80 us Metal)
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4. Reconstruct w' from hint + UseHint (~5 us NEON, ~12 us Metal)
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5. SHAKE256 of (mu || w1 encoded) -> compare against c_tilde (~2 us NEON,
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~12 us Metal)
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Total: ~42 us NEON vs ~122 us Metal per thread. At N=4096, NEON-CPU
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total = 172 ms; Metal total = 122 us * 4096 / 4096 parallel threads
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= 122 us... but dispatch overhead = ~5ms, so wall-clock total is
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~5ms + (122 us / occupancy). M1 Max's 32-core GPU runs ~96 threads
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concurrently per core (3072 in flight), so 4096 threads = 1.33 waves
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~= 200 us of in-kernel work + 5 ms dispatch. **~5.2 ms vs 172 ms NEON
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gives ~33x at N=4096 -- IF Metal SHAKE256 weren't 5x slower than NEON
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SHA3.** The 5x slowdown on the SHAKE-dominated path narrows the
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expected speedup to ~7x at N=4096, which is meaningful but the kernel
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emission complexity to ship full SHAKE256 in Metal (~1500 LOC, similar
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shape to keccak_batch v0.63) is queued for a future pass.
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dGPU H100 closes this gap because:
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1. SHAKE3 Hopper has dedicated permutation-friendly arithmetic.
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2. SM count scales the parallelism ceiling 4x.
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3. PCIe dispatch is amortised at ~0.5ms (vs 1.4ms M1 Metal-system).
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## dGPU residual
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CUDA port pending in `lux/crypto/mldsa/gpu/cuda/`. The kernel skeleton
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in `luxcpp/crypto/mldsa/gpu/metal/mldsa_batch.metal` is the architectural
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template; the CUDA emission ships the full FIPS-204 verify body.
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## Files
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- Kernel: `luxcpp/crypto/mldsa/gpu/metal/mldsa_batch.metal`
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- Driver: `luxcpp/crypto/mldsa/gpu/metal/mldsa_batch_driver.mm`
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- Test: `luxcpp/crypto/mldsa/test/mldsa_metal_test.cpp`
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- Bench: `luxcpp/crypto/mldsa/test/mldsa_metal_bench.cpp`
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- Go bridge: `lux/crypto/mldsa/gpu.go`
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- Go batch: `lux/crypto/mldsa/batch.go`
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# ML-KEM batch decap benchmarks
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**Hardware:** Apple M1 Max, macOS 26.4
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**Status:** Metal kernel skeleton (deferred to host on Apple Silicon).
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Same precedent as the mldsa_batch sibling and `aivm v0.59` / V2 EVM kernel.
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The kernel returns result code `2` (deferred) per thread on M1; host falls
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back to CPU decap. dGPU port (CUDA H100/Ada) where the skeleton expands
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into the full FIPS-203 decap pipeline is queued in LP-137 §47.
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## Dispatch overhead sweep (median microseconds per call)
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| N | Dispatch_us |
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|------|-------------|
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| 1 | 1297 us |
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| 16 | 1319 us |
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| 64 | 1442 us |
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| 256 | 1619 us |
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| 1024 | 2307 us |
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| 4096 | 3964 us |
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Same shape as mldsa: ~1.3ms floor + roughly linear growth from buffer
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copy. Slightly cheaper than mldsa because the per-input record sizes
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are smaller (2400 + 1088 = 3488 bytes/op vs 1952 + 64 + 3320 = 5336
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bytes/op for mldsa).
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## M1 ceiling rationale
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ML-KEM-768 decapsulation per-input serial work on M1 Max:
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1. K-PKE decrypt: 3 NTTs + matvec + INTT (~12 us NEON, ~30 us Metal)
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2. SHA3-512 of (m || H(pk)) -- 64+32 byte input (~1 us NEON, ~5 us Metal)
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3. SHAKE256 of (z || c) for implicit rejection -- 32+1088 byte input
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(~3 us NEON, ~15 us Metal)
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4. Re-encrypt + constant-time compare (~10 us NEON, ~25 us Metal)
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Total: ~26 us NEON vs ~75 us Metal per thread. SHA3/SHAKE chains dominate
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~50% of Metal-side work; same Apple Silicon SHA3 hardware-vs-Metal-emit
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gap as mldsa.
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At N=4096: NEON total = 106 ms; Metal aggregate = 75 us * 1.33 waves +
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4ms dispatch ~= 4.1 ms. **Expected dGPU win = ~25x at N=4096.** On M1
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Max specifically the SHAKE/SHA3 emit overhead narrows this to ~6-8x
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expected; CUDA kernel ship will close that gap (sibling task).
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## dGPU residual
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CUDA port pending in `lux/crypto/mlkem/gpu/cuda/`. The Metal skeleton is
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the architectural template.
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## Files
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- Kernel: `luxcpp/crypto/mlkem/gpu/metal/mlkem_batch.metal`
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- Driver: `luxcpp/crypto/mlkem/gpu/metal/mlkem_batch_driver.mm`
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- Test: `luxcpp/crypto/mlkem/test/mlkem_metal_test.cpp`
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- Bench: `luxcpp/crypto/mlkem/test/mlkem_metal_bench.cpp`
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- Go bridge: `lux/crypto/mlkem/gpu.go`
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- Go batch: `lux/crypto/mlkem/batch.go`
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